The Compute 100 — Thursday July 23, 2026

GMI Cloud Partnership

GMI Cloud announced a strategic compute collaboration with Nvidia, committing $500M in capex to expand capacity, and disclosed a nine-figure contract with an unnamed frontier AI enterprise. The announcement lands days after Bloomberg reported the company is separately seeking a $635M GPU-backed loan. Together, the two data points show a neocloud stretching its balance sheet aggressively to fund expansion ahead of confirmed revenue — a strategy that works only as long as GPU-backed credit stays available and utilization holds. (PR Newswire)

Crusoe Partnership

Crusoe and ON.energy will deploy 5 gigawatts of ON.energy's AI UPS medium-voltage power systems across multiple Crusoe hyperscale campuses, with commissioning starting this year and extending into 2027. The system decouples data centers from grid faults and absorbs the synchronized load swings that large GPU training clusters put on local grids. Power reliability, not chip supply, is now the binding constraint on how fast neoclouds can bring capacity online — this is Crusoe locking in the electrical infrastructure to match its compute ambitions. (Crusoe Newsroom)

Poolside Launch

Poolside released Laguna S 2.1, a 118B-parameter open-weight coding model it says matches or beats larger rivals — including DeepSeek-V4-Flash and Nvidia's Nemotron 3 Ultra — on Terminal-Bench 2.1 and SWE-Bench Pro, while running on a single Nvidia DGX Spark. Weights are posted to Hugging Face under an open license. The release is a capability and efficiency claim aimed at justifying Poolside's reported $12B valuation talks with Nvidia, and evidence that smaller, well-trained models are closing the gap with frontier-scale ones on coding tasks specifically. (VentureBeat)

Google $341.91 ▼ 1.2% Mkt Cap: $4.17T

Google raised full-year 2026 capex guidance to $195B–$205B, up from $180B–$190B, as free cash flow turned negative for the quarter; CFO Anat Ashkenazi says demand still outpaces what Google can build, per CNBC.

Researchers at the National University of Singapore published CIMERA, a chiplet-based inference accelerator that integrates compute directly into the interconnect and memory rather than treating them as separate stages, aimed squarely at the memory-bandwidth wall that constrains LLM serving, per the arXiv paper. The design combines compute-in-memory with mixed-precision and nonvolatile-memory support for KV-cache handling, and has been accepted to the IEEE AICAS 2026 conference. It is one more data point that the next efficiency gains in inference hardware are coming from architecture that blurs the line between compute, memory, and interconnect — not from process-node shrinks alone — which matters directly for any startup or hyperscaler chip program betting on where the next order of magnitude comes from.