Huawei semiconductor chief He Tingbo presented the Tau (τ) Scaling Law at the IEEE International Symposium on Circuits and Systems in Shanghai today — a framework that substitutes time-domain optimization (reducing signal propagation delays across device, circuit, chip, and system levels) for geometric transistor scaling, and requires none of the ASML EUV equipment Huawei cannot buy. The company's fall 2026 Kirin chips will be the first commercial implementation of the associated LogicFolding architecture; Huawei projects 1.4nm-equivalent transistor density by 2031, three years behind TSMC's 2028 target. SMIC already has DUV tooling sufficient to produce 1.6 million 7nm-class logic dies this year — LogicFolding is an architectural density multiplier layered on a manufacturing base that US export controls have not contained — and the fall Kirin benchmarks will be the first external signal of how much density gain the approach actually delivers.
US markets closed Mon May 25 — Memorial Day · Prices reflect Fri May 22
MRVL rose 2.96% on Friday as investors positioned ahead of Wednesday's Q1 FY2027 earnings, where the company has guided $2.4B ±5% in revenue (27% YoY at the midpoint). Data center revenue is now 74% of Marvell's mix, powered by custom XPU designs for AWS Trainium, Microsoft Maia, and a third unnamed hyperscaler — making Marvell the cleanest single-stock expression of the custom silicon shift away from merchant GPU architectures. The move also sets up May 27's print on a two-day pre-Computex timeline where every major Marvell customer will be in Taipei.
AMD surged 3.99% on Friday, touching an intraday all-time high of $481.41, as Lisa Su's $10B Taiwan ecosystem investment continued to drive investor positioning. The capital goes toward H2 2026 delivery of the Helios rack-scale platform with Instinct MI450X GPUs, and development of EFB (Elevated Fanout Bridge) 2.5D packaging for Venice EPYC CPUs with partners ASE and SPIL. AMD is competing directly with Nvidia for TSMC CoWoS packaging allocation — the packaging constraint, not process silicon, is the binding variable for both companies.
TSMC ended Friday marginally lower as supply chain focus shifted to Vera Rubin ramp timing. CoWoS capacity is scaling from ~35,000 wafers/month in late 2024 to a projected 130,000–140,000 by year-end, with Nvidia holding roughly 60% of that allocation — making packaging throughput the rate-limiting variable in the H2 AI compute cycle. AMD's $10B Taiwan commitment reinforces that advanced packaging access, not process nodes, is now the primary competitive battleground.
Honeywell's quantum computing unit set its IPO price range at $45–$50 per share today, targeting a $12.7B valuation on Nasdaq (QNT) and raising up to $1.05B on 21.05M shares. Honeywell retains 49.1% voting power post-IPO; J.P. Morgan and Morgan Stanley are joint lead underwriters. The $12.7B target is up from the $10B valuation set in Quantinuum's September 2025 funding round — the quantum computing IPO market is testing whether the Cerebras comp holds for non-GPU hardware in the current cycle.
AmCham India and Applied Materials released a joint report today identifying India's electricity grid as the single largest constraint on national AI infrastructure ambitions, proposing coordinated investment across grid resilience, energy-efficient compute supply chains, and semiconductor manufacturing as three interdependent pillars. The report lands as India accelerates its semiconductor incentive programs and positions itself as an alternative to China in global supply chain diversification — power availability is now the binding constraint on whether that positioning converts to actual fab and datacenter deployments. Watch India Semiconductor Mission policy updates and state-level power infrastructure timelines for the pace of resolution.
Jensen Huang at Computex on Saturday called elevated memory prices "a very important form of inflation" that will materially affect consumer electronics — the first time Nvidia has framed HBM scarcity as a macro consumer concern rather than a hyperscaler allocation problem. TSMC is simultaneously ramping CoWoS advanced packaging from ~35,000 wafers/month in late 2024 to a projected 130,000–140,000 by year-end, with Nvidia securing roughly 60% of that capacity — but Blackwell tail production and Vera Rubin ramp-up overlap in H2 means demand continues to outpace even that expansion. Watch Micron and SK Hynix capacity commentary in coming quarters for signals on when HBM supply growth begins to stabilize pricing.
US equity markets reopen after Memorial Day. Asian and European markets have been trading normally through the weekend — pre-Computex announcements from Taiwan may already be moving when New York opens Tuesday. Quantinuum (QNT) is also expected to begin trading on Nasdaq following tonight's IPO pricing.
Marvell Technology (MRVL) reports Q1 FY2027 earnings. Guided $2.4B ±5% revenue (27% year-over-year at the midpoint). Marvell designs XPU accelerators for three of the five largest US hyperscalers and is the bellwether for the custom silicon market. A guide raise or program expansion signals continued acceleration in bespoke AI accelerator demand; any sign of slippage reframes the hardware diversification narrative.
Computex 2026 (June 2–5) opens with a keynote lineup that extends well beyond Nvidia: Intel CEO Lip-Bu Tan presents the full 18A product stack — Panther Lake handhelds, Nova Lake 52-core desktop, and 288-core Clearwater Forest Xeon — the first time Intel has had chips in every compute category on a single node in over a decade. Qualcomm CEO Cristiano Amon and Marvell CEO Matt Murphy also keynote. Watch Intel's foundry customer disclosures: Apple and Amazon are in active discussions, and a named hyperscaler win at Computex would mark a genuine inflection in the TSMC-alternative narrative.